Multiplexers are electronic circuits which are used to combine two or more input data streams into one output data stream with appropriate higher bit rate. A multiplexer is a basic digital building block used in various applications ranging from data communication to telecommunication and data processing circuits like central processing units (CPU).
There are several approaches to implement electrical multiplexers. All of them rely on some sort of bipolar transistors or field effect transistors (FET) used as switches. By choosing different circuit topologies the speed performance of the multiplexer can be optimized. However, the finite switching speed of the available transistors will always be the limiting factor.
An embodiment of a conventional 2:1 multiplexer is shown in FIG. 1. The multiplexer comprises a so called Gilbert cell, which is controlled by a control or clock signal clk and switches depending on the clock signal clk either a first digital input signal C1 or a second digital input signal C2 to the multiplexer output OUT. For this purpose, the Gilbert cell includes switching transistors 1 to 6 and resistors 7 to 9. If for example the level of the clock signal clk is low and therefore the level of the inverted clock signal {overscore (clk)} is high, the transistor 2 is nonconducting while the transistor 3 is conducting. In this case, only the second input signal C2 is switched to the output OUT. If the level of the clock signal clk is high, only the first input signal C1 is switched to the output OUT. As already mentioned, the switching speed of the multiplexer is limited because of the finite switching speeds of the transistors 1 to 6.
Using indium phosphide high electron mobility transistors (InP HEMT) a multiplexer with a bite rate of 90 Gb/s has been demonstrated in T. Suzuki, et. al., “A 90 Gb/s 2:1 Multiplexer IC in InP HEMT Technology”, ISSCC 2002 Session 11, pp. 192–193, 2002. The speed limit for more conventional complementary metal oxide semiconductor (CMOS) devices is significantly lower due to the slower switching speed of CMOS devices compared to InP HEMTs.
EP0305771 A2, U.S. Pat. No. 5,789,966, U.S. Pat. No. 5,425,022 show examples of prior art multiplexers.